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STM6717/6718/6719/6720 STM6777/6778/6779/6780
Dual/triple ultra-low voltage supervisors with push-button reset (with delay option)
Features
Primary supply (VCC1) monitor. Fixed (factory-programmed) reset thresholds: 4.63 V to 1.58 V Secondary supply (VCC2) monitor (STM6717/18/19/20/77/78) Fixed (factory-programmed) reset thresholds: 3.08 V to 0.79 V Tertiary supply monitor (using externally adjustable RSTIN): 0.626 V internal reference RST outputs (push-pull or open drain); state guaranteed if VCC1 or VCC2 0.8 V Reset delay time (trec) on power-up: 13.2 ms, 210 ms, 900 ms (typ) Manual reset input (MR) Optional delayed manual reset input (MRC) with external capacitor (STM6777/78/79/80) Low supply current - 11 A (typ), VCC1 = VCC2 = 3.6 V Operating temperature: -40 C to 85 C (industrial grade) Device summary
Monitored voltages Part number STM6717 STM6718 STM6719 STM6720 STM6777 STM6778 STM6779 STM6780 VCC1 VCC2 RSTIN Manual reset Delayed MR input (MR) pin (MRC) Reset output (RST) Active-low (push-pull) Active-low (open drain) Package
SOT23-5 (WY)

SOT23-6 (WB)
Table 1.
WY WY WB WB WB WB WB WB
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www.st.com 1
Contents
STM6717/6718/6719/6720/STM6777/6778/6779/6780
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1.1 1.1.2 1.1.3 1.1.4 1.1.5 1.1.6 1.1.7 Active-low, push-pull reset output (RST) - STM6718/20/78/80 . . . . . . . . 7 Active-low, open drain reset output (RST) - STM6717/19/77/79 . . . . . . . 7 Push-button reset input (MR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Manual reset delay input (MRC) - STM6777/78/79/80) . . . . . . . . . . . . . . 8 Primary supply voltage monitoring input (VCC1) . . . . . . . . . . . . . . . . . . . 8 Secondary supply voltage monitoring input (VCC2) . . . . . . . . . . . . . . . . . 8 Adjustable reset comparator input (RSTIN; STM6719/20/79/80) . . . . . . 8
2
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1 Applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3 4 5 6 7 8
Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 tMLMH minimum pulse width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 SOT23-5 - 5-lead small outline transistor package mechanical data. . . . . . . . . . . . . . . . . 23 SOT23-6 - 6-lead small outline transistor package mechanical data. . . . . . . . . . . . . . . . . 24 Carrier tape dimensions for SOT23-5L and SOT23-6L . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Marking description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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List of figures
STM6717/6718/6719/6720/STM6777/6778/6779/6780
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Logic diagram (STM6717/18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Logic diagram (STM6777/78) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Logic diagram (STM6719/20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Logic diagram (STM6779/80) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 STM6717/18 SOT23-5 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 STM6777/78 SOT23-6 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 STM6719/20 SOT23-6 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 STM6779/80 SOT23-6 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 STM67xx interface to processor with bi-directional reset pins . . . . . . . . . . . . . . . . . . . . . . 10 Ensuring RST valid to VCC = 0 (active-low, push-pull outputs). . . . . . . . . . . . . . . . . . . . . . 10 Supply current vs. temperature (VCC1 = 5.5 V; VCC2 = 3.6 V) . . . . . . . . . . . . . . . . . . . . . . 11 Supply current vs. temperature (VCC1 = 3.6 V; VCC2 = 2.75 V) . . . . . . . . . . . . . . . . . . . . . 11 Supply current vs. temperature (VCC1 = 3.0 V; VCC2 = 2.0 V) . . . . . . . . . . . . . . . . . . . . . . 12 Supply current vs. temperature (VCC1 = 2.0 V; VCC2 = 1.0 V) . . . . . . . . . . . . . . . . . . . . . . 12 Normalized VCC reset time-out period vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Maximum VCC transient duration vs. reset threshold overdrive . . . . . . . . . . . . . . . . . . . . . 13 Normalized VRST1 threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Normalized VRST2 threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Reset input threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 VCC1-to-reset delay vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Reset input-to-reset output delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 MR-to-reset output delay vs. temperature (VCC1 = 3.6V) . . . . . . . . . . . . . . . . . . . . . . . . . . 16 AC testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 MR timing waveform (STM6717/18/19/20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 MR timing waveform (STM6777/78/79/80) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 SOT23-5 - 5-lead small outline transistor package mechanical drawing . . . . . . . . . . . . . . 23 SOT23-6 - 6-lead small outline transistor package mechanical drawing . . . . . . . . . . . . . . 24 Carrier tape for SOT23-5L and SOT23-6L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
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Description
1
Description
The STM6717/18/19/20 and STM6777/78/79/80 supervisors are a family of low-voltage/lowsupply current processor (micro or DSP) supervisors, designed to monitor two (or three) system power supply voltages. They are targeted at applications such as set-top boxes (STBs), portable, battery-powered systems, networking, and communication systems. All device options have a push-button-type manual reset input (MR). The STM6777/78/79/80 also includes an option which enables the user to delay the start of the manual reset process from 6 s (MRC pin left open) or more with external capacitor. The delay is implemented by connecting the appropriately sized capacitor between the MRC pin and VSS (typical 4 s delay with a 3.3 F capacitor, see Table 7 on page 21). Two of the three supplies monitored (VCC1 and VCC2) have fixed (customer-selectable, factory-trimmed) thresholds (VRST1 and VRST2). The third voltage is monitored using an externally adjustable RSTIN threshold (0.626 V internal reference). If any of the three monitored voltages drop below its factory-trimmed or adjustable thresholds, or if MR is asserted to logic low, a RST is asserted (driven low). Once asserted, RST is maintained at low for a minimum delay period (trec) after ALL supplies rise above their respective thresholds and MR returns to high. These devices are guaranteed to be in the correct reset output logic state when VCC1 and/or VCC2 is greater than 0.8 V. These devices are available in standard 5-pin or 6-pin SOT23 packages (see Table 1 on page 1).
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Description
STM6717/6718/6719/6720/STM6777/6778/6779/6780
Figure 1.
Logic diagram (STM6717/18)
VCC2 VCC1
Figure 2.
Logic diagram (STM6777/78)
VCC2 VCC1
MRC MR STM6717 STM6718 RST MR STM6777 STM6778 RST
VSS
AI10413
VSS
AI10415
Figure 3.
Logic diagram (STM6719/20)
VCC2 VCC1
Figure 4.
Logic diagram (STM6779/80)
VCC
RSTIN RSTIN MR STM6719 STM6720 RST MRC MR STM6779 STM6780 RST
VSS
AI10414
VSS
AI10416
Table 2.
MR MRC RST VCC1 VCC2 RSTIN VSS
Signal names
Push-button reset input Manual reset delay input Active-low reset output Primary supply voltage input Secondary supply voltage input Adjustable reset comparator input Ground
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Description
Figure 5.
STM6717/18 SOT23-5 connections
Figure 6.
STM6777/78 SOT23-6 connections
RST VSS MR
1 2 3
5
VCC1
RST VSS
1 2 3
6 5 4
VCC1 MRC VCC2
4
VCC2
MR
AI10417
AI10418
Figure 7.
STM6719/20 SOT23-6 connections
Figure 8.
STM6779/80 SOT23-6 connections
RST VSS MR
1 2 3
6 5 4
VCC1 RSTIN VCC2
RST VSS MR
1 2 3
6 5 4
VCC1 RSTIN MRC
AI10419
AI10420
1.1
1.1.1
Pin descriptions
Active-low, push-pull reset output (RST) - STM6718/20/78/80
The RST pin is driven low and stays low whenever VCC1 or VCC2 or RSTIN falls below its factory-trimmed or adjustable reset threshold or when MR goes to logic low. It remains low for trec after ALL supply voltages being monitored rise above their reset thresholds and MR goes from low to high. (Push-pull outputs are referenced to VCC1.)
1.1.2
Active-low, open drain reset output (RST) - STM6717/19/77/79
The RST pin is driven low and stays low whenever VCC1 or VCC2 or RSTIN falls below its factory-trimmed or adjustable reset threshold or when MR goes to logic low. It remains low for trec after ALL supply voltages being monitored rise above their reset thresholds and MR goes from low to high. Connect an external pull-up resistor to VCC1. A 10 k pull-up resistor should be sufficient for most applications.
1.1.3
Push-button reset input (MR)
When MR goes low the RST output is driven low. RST remains low as long as MR is low and for trec after MR returns to high. This active-low input has an internal 50 k pull-up resistor to
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Description
STM6717/6718/6719/6720/STM6777/6778/6779/6780 VCC1. It can be driven from a TTL or CMOS logic line, or with open drain/collector outputs, or connected to VSS through a switch. If unused, leave this pin open or connect it to VCC1. Connect a normally open momentary switch from MR to VSS; external debounce circuitry is not required. (If MR is driven from long cables or if the device is used in noisy environments, connecting a 0.1F capacitor from MR to VSS provides additional noise immunity.
1.1.4
Manual reset delay input (MRC) - STM6777/78/79/80)
This pin is either left open or connected to VSS via a capacitor. By selecting the appropriate capacitor, the manual reset process, initiated by pressing the push-button manual reset input, can be delayed by any value from 6 s or more (see Table 7 on page 21).
1.1.5
Primary supply voltage monitoring input (VCC1)
It also is the input for the primary reset threshold monitor. Available fixed (customerselectable, factory-programmed) reset thresholds include 4.63 V to 1.58 V.
1.1.6
Secondary supply voltage monitoring input (VCC2)
This function is available on the STM6717/18/19/20/77/78. Fixed (customer-selectable, factory-programmed) reset thresholds include 3.08 V to 0.79 V.
1.1.7
Adjustable reset comparator input (RSTIN; STM6719/20/79/80)
This is a high impedance input. RST is driven low when the voltage at the RSTIN pin falls below 0.626 V (internal reference voltage at this comparator). The monitored voltage reset threshold is set with an external resistor-divider network. Table 3. Pin functions
Pin STM6717 STM6718 1 3 -- 5 4 -- 2 STM6719 STM6720 1 3 -- 6 4 5 2 STM6777 STM6778 1 3 5 6 4 -- 2 STM6779 STM6780 1 3 4 6 -- 5 2 RST MR MRC VCC1 VCC2 Active-low reset output Push-button reset input Manual reset delay input Primary supply voltage input Secondary supply voltage input Name Function
RSTIN Adjustable reset comparator input VSS Ground
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STM6717/6718/6719/6720/STM6777/6778/6779/6780 Figure 9. Block diagram
VCC1 VRST1 VCC2 (1) VRST2 RSTIN(2) VCC1 VREF/2 = 0.626 COMPARE COMPARE COMPARE
Description
trec Generator
RST
MR MRC(3)
Logic
AI10421
1. VCC2 input is available on STM6717/18/19/20/77/78. 2. RSTIN available only on STM6719/20/79/80. 3. MRC available only on STM6777/78/79/80.
Figure 10. Hardware hookup
From DC/DC Converter VCC2(1) VCC1 VCC1 VCC3 = (626.5mV) R1 + R2 R2
(
)
0.1F STM67xx VCC2
VCC3 0.1F R1 RSTIN(2) R2 MR Push-button Switch C MRC(3) VSS RST RST (To Processor Reset)
AI10422
1. VCC2 is available only on STM6717/18/19/20/77/78. 2. RSTIN available only on STM6719/20/79/80. 3. MRC available only on STM6777/78/79/80.
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Operation
STM6717/6718/6719/6720/STM6777/6778/6779/6780
2
2.1
Operation
Applications information
1. Interfacing to processors with bi-directional reset pins Most processors with bi-directional reset pins can interface directly to the open drain RST outputs (STM6717/19/77/79). Systems simultaneously requiring a push-pull RST output and a bi-directional reset interface can be in logic contention. To prevent this contention, connect a 4.7 k resistor between RST and the processor's reset I/O as shown in Figure 11. 2. Ensuring a valid RST output down to VCC = 0 V The STM67xx supervisors are guaranteed to be in the correct RST output logic state when VCC1 and/or VCC2 is greater than 0.8 V. In applications which require valid reset levels down to VCC = 0, a pull-down resistor to active-low outputs (push-pull only, see Figure 12) will ensure that the reset line is valid while the reset output can no longer sink or source current. This scheme does NOT work with the open drain outputs of the STM6717/19/77/79. The resistor value used is not critical, but it must be large enough not to load the reset output when VCC is above the reset threshold. For most applications, 100 k is adequate. Figure 11. STM67xx interface to processor with bi-directional reset pins
VCC2 VCC1
STM67xx To other system components
Processor
VCC1 VCC2
RST 4.7k VSS
RESET VSS
AI10425
Figure 12. Ensuring RST valid to VCC = 0 (active-low, push-pull outputs)
STM67xx
VCC1
VCC1
RST
VSS
R1
AI10426
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Typical operating characteristics
3
Note:
Typical operating characteristics
Typical values are at TA = 25 C unless otherwise noted. Figure 13. Supply current vs. temperature (VCC1 = 5.5 V; VCC2 = 3.6 V)
18 16
Supply current (A)
14 12 10 8 6 4 2 0 -40 ICC2 ITOTAL ICC1
-20
0
20
40
60
80
AI11843
Temperature (C)
Figure 14. Supply current vs. temperature (VCC1 = 3.6 V; VCC2 = 2.75 V)
18 16 14 Supply current (A) 12 10 8 6 4 2 0 -40 ICC2 ITOTAL ICC1
-20
0
20 40 Temperature (C)
60
80
AI11844
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Typical operating characteristics
STM6717/6718/6719/6720/STM6777/6778/6779/6780
Figure 15. Supply current vs. temperature (VCC1 = 3.0 V; VCC2 = 2.0 V)
18 16
Supply current (A)
14 12 10 8 6 4 2 ICC2 0 -40 -20 0 20 40 60 80 ITOTAL
ICC1
Temperature (C)
AI11845
Figure 16. Supply current vs. temperature (VCC1 = 2.0 V; VCC2 = 1.0 V)
18 16
Supply current (A)
14 12 10 8 6 ICC1 4 2 0 -40 ICC2 -20 0 20 40 60 80 ITOTAL
Temperature (C)
AI11846
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Typical operating characteristics
Figure 17. Normalized VCC reset time-out period vs. temperature
1.07
1.05
Reset period
1.03
1.01
0.99
0.97 -40
-20
0
20
40
60
80
AI11847
Temperature (C)
Figure 18. Maximum VCC transient duration vs. reset threshold overdrive
Maximum VCC transient duration (s)
1000
100
10
1 1 10 100 1000
AI11848
Reset threshold overdrive (mV)
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Typical operating characteristics
STM6717/6718/6719/6720/STM6777/6778/6779/6780
Figure 19. Normalized VRST1 threshold vs. temperature
1.004
VRST1 reset threshold
1.002
1.000
0.998
0.996 -40
-20
0
20
40
60
80
AI11849
Temperature (C)
Figure 20. Normalized VRST2 threshold vs. temperature
1.004
VRST2 reset threshold
1.002
1.000
0.998
0.996 -40
-20
0
20
40
60
80
AI11850
Temperature (C)
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STM6717/6718/6719/6720/STM6777/6778/6779/6780 Figure 21. Reset input threshold vs. temperature
630
Typical operating characteristics
Reset input threshold (mV)
629
628
627
626
625
624 -40 -20 0 20 40 60 80
AI11851
Temperature (C)
Figure 22. VCC1-to-reset delay vs. temperature
48
VCC1-to-reset delay (s)
44
40
36
32
28 -40 -20 0 20 40 60 80
AI11852
Temperature (C)
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Typical operating characteristics
STM6717/6718/6719/6720/STM6777/6778/6779/6780
Figure 23. Reset input-to-reset output delay vs. temperature
29.0
RSTIN-to-reset output delay (s)
28.5 28.0 27.5 27.0 26.5 26.0 25.5 25.0 -40 -20 0 20 40 60 80
AI11853
Temperature (C)
Figure 24. MR-to-reset output delay vs. temperature (VCC1 = 3.6V)
500
MR-to-reset output delay (ns)
480
460
440
420
400 -40 -20 0 20 40 60 80
AI11854
Temperature (C)
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Maximum rating
4
Maximum rating
Stressing the device above the rating listed in the Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 4.
Symbol TSTG TSLD(1) VIO VCC1, VCC2 IIO PD
Absolute maximum ratings
Parameter Storage temperature (VCC off) Lead solder temperature for 10 seconds Input or output voltage Supply voltage Input or output current (all pins) SOT23-5 Power dissipation SOT23-6 675 mW Value -55 to 150 260 -0.3 to VCC1 + 0.3 -0.3 to VCC2 + 0.3 -0.3 to 7.0 20 654 Unit C C V V V mA mW
1. Reflow at peak temperature of 260 C. The time above 255 C must not exceed 30 seconds.
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DC and AC parameters
STM6717/6718/6719/6720/STM6777/6778/6779/6780
5
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in Table 5: Operating and AC measurement conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 5. Operating and AC measurement conditions
Parameter VCC supply voltage Ambient operating temperature (TA) Input rise and fall times Input pulse voltages Input and output timing ref. voltages STM67xx 0.8 to 5.5 -40 to 85 5 0.2 to 0.8VCC 0.3 to 0.7VCC Unit V C ns V V
Figure 25. AC testing input/output waveforms
0.8VCC 0.7VCC 0.3VCC
AI02568
0.2VCC
Figure 26. MR timing waveform (STM6717/18/19/20)
tMLMH MR tMLRL RST trec
AI10423a
Figure 27. MR timing waveform (STM6777/78/79/80)
tMLMH MR tMLRL RST trec
AI10424c
(1)
1. By connecting a certain capacitor between the MRC pin and VSS, the RST can be delayed from 6 s or more (tMLMH, see Table 7 on page 21).
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STM6717/6718/6719/6720/STM6777/6778/6779/6780 Table 6.
Sym VCC ICC1
DC and AC parameters
DC and AC characteristics
Alternative Description Operating voltage VCC1 supply current VCC1 < 5.5 V, all I/O pins open VCC1 < 3.6 V, all I/O pins open VCC2 < 3.6 V, all I/O pins open VCC2 < 2.75 V, all I/O pins open 0 V = VIN = VCC VCC1 > VRST1, VCC2 > VRST2; RST not asserted VCC1 or VCC2 0.8 V, ISINK = 1 A, RST asserted VCC1 or VCC2 1.0 V, ISINK = 50 A, RST asserted -1 Test condition(1) Min 0.8 12 8 3 2.5 Typ Max 5.5 35 23 9 7 +1 0.5 0.3 0.3 0.3 0.3 0.4 0.8VCC1 0.8VCC1 0.8VCC1 Unit V A A A A A A V V V V V V V V
ICC2 ILI
(2)
VCC2 supply current Input leakage current Open drain RST output leakage current
ILO
VOL
Output low voltage (RST; push-pull or open drain)
VCC1 or VCC2 1.2 V, ISINK = 100 A, RST asserted VCC1 or VCC2 2.7 V, ISINK = 1.2 mA, RST asserted VCC1 or VCC2 4.5 V, ISINK = 3.2 mA, RST asserted VCC1 1.8 V, ISOURCE = 200 A, RST not asserted
VOH
Output high voltage (RST; push-pull only)
VCC1 2.7 V, ISOURCE = 500 A, RST not asserted VCC1 4.5 V, ISOURCE = 800 A, RST not asserted
tR(3) Reset thresholds
Push-pull RST rise time (STM6718/20/78/80)
Rise time measured from 10% to 90% of VCC; CL = 5 pF, VCC = 3.3 V
5
25
ns
L (falling) M (falling) T (falling) S (falling) VRST(4) VTH1 VCC1 reset threshold R (falling) Z (falling) Y (falling) W (falling) V (falling)
4.500 4.250 3.000 2.850 2.550 2.250 2.125 1.620 1.530
4.625 4.750 4.375 4.500 3.075 3.150 2.925 3.000 2.625 2.700 2.313 2.375 2.188 2.250 1.665 1.710 1.575 1.620
V V V V V V V V V
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DC and AC parameters Table 6.
Sym
STM6717/6718/6719/6720/STM6777/6778/6779/6780
DC and AC characteristics (continued)
Alternative Description Test condition(1) T (falling) S (falling) R (falling) Z (falling) Y (falling) W (falling) V (falling) Min 3.000 2.850 2.550 2.250 2.125 1.620 1.530 1.350 1.275 1.080 1.020 0.895 0.845 0.810 0.765 Typ Max Unit V V V V V V V V V V V V V V V % s s 280 17.6 1200 ms
3.075 3.150 2.925 3.000 2.625 2.700 2.313 2.375 2.188 2.250 1.665 1.710 1.575 1.620 1.388 1.425 1.313 1.350 1.110 1.140 1.050 1.080 0.925 0.955 0.875 0.905 0.833 0.855 0.788 0.810 0.5 20 20
VRST2
(4)
VTH2
VCC2 reset threshold
I (falling) H (falling) G (falling) F (falling) K (falling) J (falling) E (falling) D (falling)
VHYST
Reset threshold hysteresis
Referenced to VRST typical VCC1 = (VRST1 + 100 mV) to (VRST - 100 mV) VCC2 = (VRST2 + 75 mV) to (VRST2 - 75 mV) blank 140 8.8 600
tRD
VCC to RST delay
210 13.2 900
trec
tRP
RST pulse width
B G
Adjustable reset comparator input (STM6719/20/79/80) VRSTIN IRSTIN RSTIN input threshold RSTIN input current RSTIN hysteresis tRSTIND RSTIN to RST output delay VRSTIN to (VRSTIN - 30 mV) 611 -25 3 22 626.5 642 +25 mV nA mV s
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STM6717/6718/6719/6720/STM6777/6778/6779/6780 Table 6.
Sym
DC and AC parameters
DC and AC characteristics (continued)
Alternative Description Test condition(1) Min Typ Max Unit
Manual (push-button) reset input VIL VIH MR minimum pulse width (STM6717/18/19/20) tMLMH tMR MR minimum pulse width (STM6777/78/79/80) MR to RST output delay MR glitch immunity (STM6717/18/19/20) MR pull-up resistance 25 MRC connected via capacitor to VSS(5) 0.3VC MR input voltage 0.7VCC1 1 6 200 100 50 80
C1
V V s s ns ns k
tMLRL
tMRD
1. Valid for ambient operating temperature: TA = -40 to 85 C; VCC1 = 0.8 to 5.5 V and VCC2 = 0.8 to 3.6 V (except where noted). 2. Input leakage for the MRC pin is not tested. 3. Guaranteed by design. 4. The leakage current measured on the RST pin is tested with the reset de-asserted (output high impedance). 5. Selecting the appropriate external capacitor (preferably less than 100 pF) allows systems designers to vary the minimum delay from 6s (MRC pin left open) or more (see Table 7).
Table 7.
VCC1
tMLMH minimum pulse width
Capacitor value(1) 100 pF 0.1 F 120 ms 122 ms 125 ms 129 ms 130 ms 2.2 F 2.6 s 2.7 s 2.7 s 2.8 s 2.8 s 3.3 F 4.0 s 4.0 s 4.1 s 4.2 s 4.3 s 4.7 F 5.6 s 5.8 s 5.9 s 6.0 s 6.1 s 6.8 F 8.2 s 8.3 s 8.5 s 8.7 s 8.8 s
1.6 V 2.0 V 3.0 V 4.0 V 5.0 V
1. At 25 C (typical)
120 s 122 s 125 s 128 s 130 s
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Package mechanical data
STM6717/6718/6719/6720/STM6777/6778/6779/6780
6
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark.
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STM6717/6718/6719/6720/STM6777/6778/6779/6780
Package mechanical data
Figure 28. SOT23-5 - 5-lead small outline transistor package mechanical drawing
E A1
1
e e1 5x b 5x
0.20
M
D
CAB
A
C 0.10 C
A2 A
Datum A 0.20
C
B
L E1
0133778
Note:
Drawing is not to scale. Table 8.
Symb Min A A1 A2 b C D E E1 e e1 L Q N -- -- 0.90 0.30 0.08 -- -- -- -- -- 0.30 0 Typ -- -- 1.15 -- -- 2.90 2.80 1.60 0.95 1.90 0.45 4 5 Max 1.45 0.15 1.30 0.50 0.22 -- -- -- -- -- 0.60 8 Min -- -- 0.035 0.012 0.003 -- -- -- -- -- 0.012 0 Typ -- -- 0.045 -- -- 0.114 0.110 0.063 0.037 0.075 0.018 4 5 Max 0.057 0.006 0.051 0.020 0.009 -- -- -- -- -- 0.024 8
SOT23-5 - 5-lead small outline transistor package mechanical data
mm inches
Note:
Dimensions per JEDEC SOT/SOP product outline MO-178C, variation AA
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Package mechanical data
STM6717/6718/6719/6720/STM6777/6778/6779/6780
Figure 29. SOT23-6 - 6-lead small outline transistor package mechanical drawing
E A1
1
e e1 D
6x b
0.10
M
6x
CAB A C 0.10 C
A2 A
Datum A 0.20
C
B
L E1
7049714
Note:
Drawing is not to scale. Table 9.
Symb Min A A1 A2 b C D E E1 e e1 L Q N -- -- 0.90 0.30 0.08 -- -- -- -- -- 0.30 0 Typ -- -- 1.15 -- -- 2.90 2.80 1.60 0.95 1.90 0.45 4 6 Max 1.45 0.15 1.30 0.50 0.22 -- -- -- -- -- 0.60 8 Min -- -- 0.035 0.012 0.003 -- -- -- -- -- 0.012 0 Typ -- -- 0.045 -- -- 0.114 0.110 0.063 0.037 0.075 0.018 4 6 Max 0.057 0.006 0.051 0.020 0.009 -- -- -- -- -- 0.024 8
SOT23-6 - 6-lead small outline transistor package mechanical data
mm inches
Note:
Dimensions per JEDEC SOT/SOP product outline MO-178C variation AB
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STM6717/6718/6719/6720/STM6777/6778/6779/6780 Figure 30. Carrier tape for SOT23-5L and SOT23-6L
Package mechanical data
P0 D T P2
E
A0 TOP COVER TAPE B0
F W
K0
CENTER LINES OF CAVITY
P1
USER DIRECTION OF FEED
AM03073v1
Note:
Part pin 1 indicator is on bottom left for shipping method "F" and is on top right for shipping method "R" see Section 7. Carrier tape dimensions for SOT23-5L and SOT23-6L
W D E P0 P2 F A0 3.23 0.10 B0 3.17 0.10 K0 1.37 0.10 P1 T Unit Bulk Qty
Table 10.
Package
8.00 1.50 SOT23-5 +0.30/ +0.10/ SOT23-6 -0.10 -0.00
1.75 4.00 2.00 3.50 0.10 0.10 0.10 0.05
4.00 0.254 mm 3000 0.10 0.013
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Part numbering
STM6717/6718/6719/6720/STM6777/6778/6779/6780
7
Table 11.
Example: Device type STM67xx
Part numbering
Ordering information scheme
STM67xx LT WY 6 F
Reset thresholds (VRST1 and VRST2) for VCC1 and VCC2 STM6717/18/19/20/77/78 (VRST1 and VRST2) STM6779/80 (VRST1 only) VRST2 Suffix VRST1 Suffix VRST1 LT 4.625 3.075 L-(1) 4.625 3.075 MS 4.375 2.925 T-(1) 2.925 MR 4.375 2.625 S-(1) 3.075 2.313 Y-(1) 2.188 TZ(1) TW(1) 3.075 1.665 V-(1) 1.575 TI 3.075 1.388 R- 2.625 3.075 1.110 Z- 2.313 TG(1) TK 3.075 0.925 TE 3.075 0.833 2.925 2.188 SY(1) 2.925 1.575 SV(1) SH(2) 2.925 1.313 2.925 1.050 SF(1) 2.925 0.875 SJ(3) 2.925 0.788 SD(3) YV 2.188 1.575 YH 2.188 1.313 YF 2.188 1.050 YJ 2.188 0.875 YD 2.188 0.788 VH 1.575 1.313 VF 1.575 1.050 VJ 1.575 0.875 VD 1.575 0.788 Reset pulse width blank: trec = 140 ms to 280 ms B: trec = 8.8 ms to 17.6 ms G: trec = 600 ms to 1200 ms Package WY = SOT23-5 WB = SOT23-6 Temperature range 6 = -40 to 85C Shipping method E = ECOPACK(R) package, tubes F = ECOPACK(R) package, tape and reel R(4) = ECOPACK(R) package, tape and reel (pin 1 at top right).
1. These are standard versions and are typically held in stock. A non-standard version may require a higher minimum volumes, and/or longer delivery times. For other options, or for more information on any aspect of this device, please contact the ST sales office nearest you. 2. Available in STM6719 version only. 3. Available in STM6717 version only. 4. Available for STM6720SY, STM6719SF and STM6719SFB versions only.
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STM6717/6718/6719/6720/STM6777/6778/6779/6780 Table 12. Marking description
VRST1 threshold (V) 2.925 2.925 2.925 3.075 3.075 3.075 2.925 2.925 3.075 2.925 3.075 3.075 2.925 2.925 3.075 2.925 2.925 3.075 2.925 3.075 2.925 2.925 3.075 2.925 3.075 3.075 2.925 2.925 3.075 2.925 3.075 3.075 2.925 2.925 3.075 VRST2 threshold (V) 0.788 0.875 1.050 1.110 1.110 1.665 1.575 2.188 2.313 1.050 1.110 1.665 1.575 2.188 2.313 1.050 1.050 1.110 1.313 1.665 1.575 2.188 2.313 1.050 1.110 1.665 1.575 2.188 2.313 1.050 1.110 1.665 1.575 2.188 2.313 Topside marking 7SD1 7SJ1 7SF1 7TG1 7TG9 7TW1 7SV1 7SY1 7TZ1 7SF2 7TG2 7TW2 7SV2 7SY2 7TZ2 7SF3 7SFB 7TG3 7SH3 7TW3 7SV3 7SY3 7TZ3 7SF4 7TG4 7TW4 7SV4 7SY4 7TZ4 7SF5 7TG5 7TW5 7SV5 7SY5 7TZ5
Part numbering
Part number STM6717SD STM6717SJ STM6717SF STM6717TG STM6717TGG STM6717TW STM6717SV STM6717SY STM6717TZ STM6718SF STM6718TG STM6718TW STM6718SV STM6718SY STM6718TZ STM6719SF STM6719SFB STM6719TG STM6719SH STM6719TW STM6719SV STM6719SY STM6719TZ STM6720SF STM6720TG STM6720TW STM6720SV STM6720SY STM6720TZ STM6777SF STM6777TG STM6777TW STM6777SV STM6777SY STM6777TZ
Bottomside marking PYWW PYWW PYWW PYWW PYWW PYWW PYWW PYWW PYWW PYWW PYWW PYWW PYWW PYWW PYWW PYWW PYWW PYWW PYWW PYWW PYWW PYWW PYWW PYWW PYWW PYWW PYWW PYWW PYWW PYWW PYWW PYWW PYWW PYWW PYWW
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Part numbering Table 12. Marking description (continued)
VRST1 threshold (V) 2.925 3.075 3.075 2.925 2.925 3.075 4.625 3.075 2.925 2.188 1.575 4.625 3.075 2.925 2.188 1.575
STM6717/6718/6719/6720/STM6777/6778/6779/6780
Part number STM6778SF STM6778TG STM6778TW STM6778SV STM6778SY STM6778TZ STM6779L STM6779T STM6779S STM6779Y STM6779V STM6780L STM6780T STM6780S STM6780Y STM6780V
VRST2 threshold (V) 1.050 1.110 1.665 1.575 2.188 2.313 -- -- -- -- -- -- -- -- -- --
Topside marking 7SF6 7TG6 7TW6 7SV6 7SY6 7TZ6 7Lx7 7Tx7 7Sx7 7Yx7 7Vx7 7Lx8 7Tx8 7Sx8 7Yx8 7Vx8
Bottomside marking PYWW PYWW PYWW PYWW PYWW PYWW PYWW PYWW PYWW PYWW PYWW PYWW PYWW PYWW PYWW PYWW
Note:
For topside marking, "7" is the family number, followed by the VRST1 threshold, VRST2 threshold and device number (1,9 = STM6717, 2 = 6718, 3 = 6719, 4 = 6720, 5 = 6777, 6 = 6778, 7 = 6779, 8 = 6780). For bottomside marking, "P" = assembly site, "Y" = 1-digit year, and "WW" = 2-digit work week.
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Revision history
8
Revision history
Table 13.
Date 18-Oct-2004 25-Oct-2004 14-Jan-2005 09-Feb-2005 08-Apr-2005 28-Jul-2005 13-Sep-2005 07-Oct-2005 07-Feb-2007 12-Jun-2007 05-Dec-2007
Document revision history
Revision 1 1.1 1.2 1.3 1.4 1.5 2 3 4 5 6 First draft Descriptive text, sales types (Table 11) Update characteristics, pin functions (Table 2) Update characteristics (Figure 9; Table 3) Update characteristics and mechanical dimensions; add table (Figure 9, 10, 27, 28, 29; Table 4, 6, 11, 8, 9) Update characteristics, reset delay (Figure 10, 27; Table 4, 6, 7, 11) Add operating characteristics; update timings, document status, Leadfree text (Figure Figure 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 26, 27; Table 11) Marked STM6779/6780 as availability request parts (Table 1, 11) Updated STM6779/6780 availability (cover page, Table 1, 11) Updated Table 11, added Table 12: Marking description. Updated cover page, Table 6, 11, and 12. Updated Features; Table 6, 8, 9, 11, 12; footnote 1 of Table 4; Section 6: Package mechanical data; added tape and reel specifications (Figure 30, Table 10, footnote 4 of Table 11); reformatted document. Changes
22-Mar-2010
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STM6717/6718/6719/6720/STM6777/6778/6779/6780
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